1. Field of the Invention
The present invention generally belongs to the field of data transmitting system frame clock synchronization. In particular, the present invention belongs to the field of synchronizing the frame clock in units/nodes of data transmitting systems.
2. Discussion of the Related Art
In many data transmission systems, a basic structure of the data transmission is built up by a frame clock signal, for example in SDH systems (SDH=synchronous digital hierarchy). What are to be understood by xe2x80x9cdataxe2x80x9d, of course, are arbitrary digital data, including audio and video data or, respectively, signals. The data embedded in the frames are transmitted with the clock frequency that amounts to a multiple of the frame clock and that has a whole-numbered, rigid frequency and phase relationship to the frame clock. A frame clock that is often employed in practice amounts to 8 kHz and the clock frequency amounts to 2.048 MHz, corresponding to a ratio of 1:256. The basic structure xe2x80x9cframe clockxe2x80x94 clock frequencyxe2x80x9d must be maintained in a data processing in order to avoid large buffer memories.
In the example under consideration, exactly 256 data bits lie between two leading edges of the 8 kHz frame clock. When the clock frequency 2.048 MHz deviates slightly from the rated value due to a disturbance, then a frequency deviation also occurs in the 8 kHz due to the coupling of the two clocks, so that exactly 256 bits again lie in a frame clock period. This relationship must always be preserved. This is assured in the data transmission by what is referred to as the frame identifier word that is sent every 256 bits. The 2.048 MHz clock is generated from the data and the 8 kHz clock is derived from the frame identifier word. The position of the individual data channels that are merged to form the 2.048 Mbit/s data stream can in turn be identified from the position of the individual data channels.
When the 2.048 MHz clock frequency of the incoming data stream is employed as comparison frequency for synchronization given a clock regeneration in, for example, a network node with the assistance of a phase locked loop, abbreviated as PLL, then an 8 kHz signal derived from the regenerated clock can have 256 different positions relative to the frame identifier word of the incoming data stream, only one single instance thereof correctly indicating the frame start. The 8 kHz frequency acquired from the frame identifier word is therefore employed as comparison frequency and the relationship to the frame identifier word is thereby automatically obtained.
FIG. 1 shows a schematic circuit of the Prior Art with whose assistance the frame clock fRxe2x80x2 of outgoing signals is synchronized to the frame clock fR of incoming signals. The phase locked loop PLL is thereby composed of a phase detector PHD, a filter FIL, a voltage-controlled oscillator VCO and a divider DIV. In order to stick with said example, the oscillator VCO supplies a frequency fTxe2x80x2 of 2.048 MHz for the output clock. This frequency fTxe2x80x2 is divided onto 8 kHz in the divider DIV in the ratio 256:1 and is supplied to an input of the phase detector, at whose other input the frame clock fR of the incoming signals is adjacent.
The divider DIV must be a synchronous divider; as a result thereof, the 8 kHz signal edge nearly coincides with a signal edge of the 2.048 MHz clock. The relative phase position of the 8 kHz clocks is defined by the selection of the phase detector PHD. An EX-OR phase detector causes a 90xc2x0 phase shift; however, a slight asymmetry in the reference voltage can already cause significant phase deviations with reference to 2.048 MHz. Given outage of the reference signal, the last frequency is therefore approximately maintained for some time. Other known phase detector circuits that synchronize to 0 phase difference are, of course, more favorable with respect to the phase difference but, given outage of the reference signal, have the property of immediately greatly detuning the clock output in terms of frequency, often up to the frequency limits of the oscillator VCO.
The circuit according to FIG. 1 of the Prior Art has a number of disadvantages:
a) Insofar as it lies in the proximity of the frame clockxe2x80x948 kHzxe2x80x94or a multiple thereof, the jitter of the frame clock signal fR is mixed down into the region of 0 Hz by mixed products at the phase detector and can then no longer be filtered out in following phase locked loops, whereby an inadmissibly high jitter accumulation can occur over the course of a data transmission link with a corresponding serial connection of phase locked loops.
b) A high filter gain is required in the loop, which in turn produces a great sensitivity to voltage fluctuations and noise voltages.
c) As mentioned above, signal disturbances at the input can lead to great frequency and voltage fluctuations.
It is an object of the present invention to provide a synchronization circuit wherein the clock derived from the data exhibits a multiple clock frequency compared to the frame clock.
It is another object of the invention to provide a synchronization circuit wherein the divider is fashioned as an adjustable divider with an adjustable division factor,
It is a further object of the invention to provide a synchronization circuit wherein a divider is connected to a frame clock phase detector for setting its division factor.
It is an additional object of the invention to provide a synchronization circuit that enables a fast resynchronization given disturbances and yields a drastic reduction of jitter.
It is yet another object of the invention to provide a synchronization circuit wherein a frame clock phase detector configured for output of a pulse that temporarily raises or lowers the division factor of the divider dependent on the maximum phase jitter of the clocks if the frame clocks deviate.
It is yet a further object of the invention to provide a synchronization circuit wherein a frame clock phase detector is supplied with the input frame clock, the
These and other objects of the invention will become apparent upon careful review of the detailed description of the preferred embodiments which is to be read in conjunction with review of the accompanying drawing figures.